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high - efficiency charger for li - ion batteries zspm4551 datasheet ? 2016 integrated device technology, inc. 1 january 29, 2016 c out l out r sense r ref battery r thm r pullup (optional) vdd r pullup (optional) vdd c vdd gnd en vtherm sw nflt vbat scl pgnd vin sda vth_ref vsense vdd zspm4551 c in brief description the zspm4551 is a dc/dc synchronous switching lithium - ion ( li - i on) b attery c harger with fully inte - grated power switches, internal compensation, and full fault protection. its switching frequency of 1mhz enables the use of small filter components, resulting in smaller board space and reduced bom costs. in full - charge constant - current mode , the regula - t ion is for constant current (cc) . once termination voltage is reached, the regulator operates in voltage mode. when the regulator is disabled ( the en pin is low), the de vice draws 10 a (typical) quiescent current. the zspm4551 includes supervisory reporting through the n flt ( i nverted f ault) open - drain output to interface other components in the system. device programming is achieved by an i2c ? * interface through the scl and sda pins. benefits ? up to 1.5a of continuous output cur rent in full - charge constant - current (cc) m ode ? high efficiency ? up to 92% with typical loads available support ? evaluation kit ? support documentation * i 2 c ? is a trademark of nxp. features ? v bat reverse - current blocking ? programmable temperature - compensated termination voltage : 3.94v to 4.18v 1% ? user programmable maximum charge current: 50ma to 1500ma ? current mode pwm control in constant voltage ? supervisor for vbat reported at the n flt pin ? input supply under - v oltage lockout ? full protection for over - current, over - temp erature , vbat over - voltage, and charging timeout ? charge status indication ? i 2 c ? program interface with eep rom registers related idt smart power products ? zspm4121 ultra - low power under - voltage switch ? zspm4141 ultra - low - power linear regulator physical characteristics ? wide input voltage range: v bat + 0.3v (3.5v min.) to 7.2v ? junction operating temperature: - 4 0c to 12 5c ? package: 16- pin p qfn (4 mm x 4 mm) zspm4551 application circuit
high - efficiency charger for li - ion batteries zspm4551 datasheet ? 2016 integrated device technology, inc. 2 january 29, 2016 typical applications ? portable battery chargers ? smart phones ? laptops ? tablet s/ e - readers vin batt current control gate drive gate drive gate drive control vbat sw oscillator ramp generator comparator error amp gnd monitor & control batt thermal control over-voltage protection vbat vin vin s en pgnd nflt c out l out battery compensation network vth_ref vtherm vref vbat r thm r ref r sense vsense current control scl sda vin vdd c vdd vdd regulator vin backgate blocking zspm4551 i2c?* interface i2c?*is a trademark of nxp. zspm4551 block diagram ordering information ordering code description package zspm4551 aa1w zspm4551 high - efficiency li - ion battery charger 16- pin pqfn / 7? reel (1000 parts) zspm4551 aa1r zspm4551 high - efficiency li - ion battery charger 16- pin pqfn / 13? reel (3300 parts) zspm4551 kit zspm4551 evaluation kit corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408- 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed t o perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for any pa rticular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third p arties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, wri tten agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its s ubsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.
zspm4551 datasheet ? 2016 integrated device technology, inc. 3 january 29, 2016 contents 1 zspm4551 characteristics ............................................................................................................................... 5 1.1. absolute maximum ratings ....................................................................................................................... 5 1.2. thermal characteristics ............................................................................................................................. 6 1.3. recommended operating conditions ....................................................................................................... 6 1.4. electrical characteristics ........................................................................................................................... 7 1.5. i 2 c? interface timing requirements ...................................................................................................... 10 2 functional description .................................................................................................................................... 11 2.1. internal protection ................................................................................................................................... 12 2.1.1. vin under - voltage lockout .............................................................................................................. 12 2.1.2. internal current limit ........................................................................................................................ 12 2.1.3. thermal shutdown ............................................................................................................................ 12 2.1.4. vbat over - voltage protection ......................................................................................................... 12 2.2. fault handling .......................................................................................................................................... 13 2.2.1. nflt pin functionality ...................................................................................................................... 13 2.2.2. other faults ...................................................................................................................................... 13 2.3. serial interface ........................................................................................................................................ 15 2.3.1. i 2 c? subaddress definition ............................................................................................................. 15 2.3.2. i 2 c? bus operation .......................................................................................................................... 15 2.4. status and configuration registers ......................................................................................................... 17 3 application circuits ......................................................................................................................................... 22 3.1. typical application circuit ....................................................................................................................... 22 3.2. selection of external components .......................................................................................................... 22 3.2.1. c out output capacitor ...................................................................................................................... 22 3.2.2. l out output inductor ......................................................................................................................... 22 3.2.3. c in bypass capacitor ........................................................................................................................ 22 3.2.4. c vdd bypass capacitor for vdd internal reference voltage output ............................................... 22 3.2.5. r sense output sensing resistor ....................................................................................................... 23 3.2.6. pull - up resistors ............................................................................................................................... 23 4 pin configuration and package ...................................................................................................................... 23 4.1. zspm4551 package dimensions ............................................................................................................ 23 4.2. pin - out assignments ............................................................................................................................... 24 4.3. pin description for 16 - pin pqfn (4 x 4 mm) .......................................................................................... 24 4.4. package markings ................................................................................................................................... 25 5 layout recommendations .............................................................................................................................. 26 5.1. multi - layer pcb layout ........................................................................................................................... 26 5.2. single - layer pcb layout ........................................................................................................................ 27 6 ordering information ...................................................................................................................................... 28 7 rela ted documents ........................................................................................................................................ 28 8 document revision history ............................................................................................................................ 29
zspm4551 datasheet ? 2016 integrated device technology, inc. 4 january 29, 2016 list of figures figure 2.1 zspm4551 block diagram ............................................................................................................... 11 figure 2.2 charging state diagram ................................................................................................................... 14 figure 2.3 subaddress in i 2 c? transmission ................................................................................................... 15 figure 2.4 i 2 c? start / stop protocol ................................................................................................................ 16 figure 2.5 i 2 c? data transmission timing ...................................................................................................... 16 figure 3.1 typical application circuit for charging a lithium - ion battery ......................................................... 2 2 figure 4.1 pqfn - 16 package dimensions ........................................................................................................ 23 figure 4.2 zspm4551 pin assignments ............................................................................................................ 24 figure 4.3 marking diagram 16 - pin pqfn (4 x 4 mm ) ...................................................................................... 25 figure 5.1 package and pcb land configuration for multi - layer pcb ............................................................ 26 figure 5.2 jedec standard fr4 multi - layer board ? cross - sectional view ................................................... 26 figure 5.3 conducting heat away from the die using an exposed pad package ............................................ 27 figure 5.4 application using a single - layer pcb ............................................................................................. 28 list of ta bles table 1.1 absolute maximum ratings ................................................................................................................ 5 table 1.2 thermal characteristics ...................................................................................................................... 6 table 1.3 recommended operating conditions ................................................................................................ 6 table 1.4 electrical characteristics .................................................................................................................... 7 table 1.5 i 2 c? interface timing characteristics .............................................................................................. 10 table 2.1 register descriptions (device address = 48 hex ) .............................................................................. 17 table 2.2 status register ? address 00 hex .................................................................................................. 17 table 2.3 configuration register config1 ? address 02 hex .......................................................................... 18 table 2.4 configuration register config2 ? address 03 hex .......................................................................... 18 table 2.5 configuration register config3 ? address 04 hex .......................................................................... 19 table 2.6 configuration register config4 ? address 05 hex .......................................................................... 19 table 2.7 configuration register config5 ? address 06 hex .......................................................................... 20 table 2.8 enable configuration register config_enable ? address 11 hex ................................................ 21 table 2.9 eeprom control register eeprom_ctrl ? address 12 hex ........................................................ 21 table 4.1 pin description .................................................................................................................................. 24
zspm4551 datasheet ? 2016 integrated device technology, inc. 5 january 29, 2016 1 zspm4551 characteristics important: stresses beyond those listed under ?absolute maximum ratings? (section 1.1 ) may cause permanent damage to the devic e. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? r ecommended o pe rating c onditions? is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. 1.1. absolute maximum ratings over operating free ? air temperature range unless otherwise noted . table 1 . 1 a bsolute maximum ratings parameter value 1) unit vin, en, nflt, scl, sda, vtherm, vth_ref, vbat, vsense - 0.3 to 8 v sw - 1 to 8.8 v vdd - 0.3 to 3.6 v operating junction temperature range, t j - 40 to 125 c storage temperature range, t stor - 65 to 150 c electrostatic discharge ? human body model 2) 2k v electrostatic discharge ? machine model 2) +/ -200 v lead temperature (soldering, 10 seconds) 260 c 1) all voltage values are with respect to network ground terminal. 2) esd testing is perform ed according to the respective jesd22 jedec standard.
zspm4551 datasheet ? 2016 integrated device technology, inc. 6 january 29, 2016 1.2. thermal characteristics table 1 . 2 thermal characteristics parameter symbol value 1) unit thermal resistance junction to air 1) ja 50 c/w 1) assumes a 4x4mm qfn - 16 in 1 in 2 area of 2 oz . copper and 25 c ambient temperature. 1.3. recommended operating conditions table 1 . 3 recommended o perating c onditions parameter symbol min typ max unit input operating voltage at vin pin v in v bat + 0.3v (3.5v min) 5.3 7.2 v sense resistor r sense 50 m ? output filter inductor typical value 1) l out 4.7 h output filter capacitor typical value 2) c out 4.7 f output filter capacitor esr c out - esr 100 m ? input supply bypass capacitor value 3) c in 3.3 10 f vdd supply bypass capacitor value 2) c vdd 70 100 130 nf operating free air temperature t a -40 85 c operating junction temperature t j -40 125 c 1) for best performance, use an inductor with a saturation current rating higher than the maximum v bat load requirement plus the inductor current ripple. 2) for best performance, use a low esr ceramic capacitor. 3) for best performance, use a low esr ce ramic capacitor. if c in is not a low esr ceramic capacitor, add a 0.1 f ceramic cap acitor in parallel to c in .
zspm4551 datasheet ? 2016 integrated device technology, inc. 7 january 29, 2016 1.4. electrical characteristics electrical c haracteristics t j = - 40c to 1 25c , vin = 5.3v, (unless otherwise noted) table 1 . 4 electrical c haracteristics parameter symbol condition min typ max unit vin supply voltage voltage input v in v bat + 0.3v (3.5v min) 5.3 7.2 v quiescent c urrent normal mode i cc- norm i load = 0a, no switching en 2.2v (high) 3 ma quiescent c urrent disabled mode i cc- - disable en = 0v 10 50 a vbat leakage leakage current from batt ery i bat - leak en = 0v, v v bat = 4.1v 10 a reverse current i bat - back vbat > vin, vbat = 4.1v, t j < 85 c 10 a vin under - voltage lockout input supply under - voltage threshold v in - uv v in i ncreasing 3. 15 v input supply under - voltage threshold hysteresis v in - uv_hyst 100 200 mv osc oscillator frequency f osc 0.9 1 1.1 mhz n flt open drain output high - level output leakage i oh - n flt v n flt = 5.3v 0.1 a low - level output voltage v ol - n flt i n flt = - 1ma 0.4 v en/scl/sda input voltage thresholds high level input voltage v ih 2.2 v low level input voltage v il 0.8 v input hysteresis ? en, scl, sda pins v hyst 200 mv
zspm4551 datasheet ? 2016 integrated device technology, inc. 8 january 29, 2016 parameter symbol condition min typ max unit input leakage ? en pin i in - en v en =vin 0.1 a v en =0v - 2.0 a input leakage ? scl pin i in - scl v scl =vin 55 a v scl =0v - 0.1 a input leakage ? sda pin i in - sda v sda =vin 0.1 a v sda =0v - 0.1 a low - level output voltage v ol - sda i sda = - 1ma 0.4 v thermal shutdown thermal shutdown junction temperature t sd 150 170 c tsd hysteresis t sd - hyst 10 c pre - charge end pre -c harge voltage threshold v prechg 2.9 3.0 3.1 v pre -c harge voltage hysteresis v pc - hyst 70 mv charge restart voltage b elow t ermination for c harging r estart v restart 100 mv charging regulator with l out =4.7 h and c out =4.7 f output current limit tolerance in full - charge mode i bat - fc i bat is u ser programmable; see table 2 . 5 . i bat - 10% i bat i bat + 10% a termination voltage tolerance in top - off mod e v bat - to i bat = 0.1c, 0 c < t j < 85 c v bat is u ser programmable; see section 2.4 . v bat - 1% v bat v bat + 1% v top - off mode time out t to 0 120 minutes full - charge timer t fc 200 1400 minutes timer accuracy t acc -10% +10% high side switch on resistance r dson i sw = - 1a, t j =25 c 200 m? low side switch on resistance i sw = 1a, t j =25 c 250 m? max imum output current i bat 1.5 a over - current detect i ocd hs switch current 2.5 a v bat over - voltage threshold v bat - ov 101% v bat 102% v bat 103% v bat maximum duty cycle duty max 98 %
zspm4551 datasheet ? 2016 integrated device technology, inc. 9 january 29, 2016 parameter symbol condition min typ max unit thermistor vth_ref o utput v oltage v vth_ref i vt_ref = 2 a to 100 a 1.8 v thermistor: 10k? temperature thresholds ? =3434k 0c v therm threshold (0c) 0c decreasing temperature 75.6 %vth_ref 0c vtherm threshold with hysteresis (10c) 0c hyst increasing temperature 66.5 %vth_ref 10c vtherm threshold (10c) 10c decreasing temperature 66.2 %vth_ref 10c vtherm threshold with hysteresis (11c) 10c hyst increasing temperature 65.4 %vth_ref 45c vtherm threshold (45c) 45c increasing temperature 34.5 %vth_ref 45c vtherm threshold with hysteresis (44c) 45c hyst decreasing temperature 35.3 %vth_ref 50c vtherm threshold (50c) 50c increasing temperature 30.8 %vth_ref 50c vtherm threshold with hysteresis (49c) 50c hyst decreasing temperature 31.5 %vth_ref 60c vtherm threshold (60c) 60c increasing temperature 24.9 %vth_ref 60c vtherm threshold with hysteresis (50c) 60c hyst decreasing temperature 30.8 %vth_ref thermistor: 100k? temperature thresholds ? =4311k 0c vtherm threshold (0c) 0c decreasing temperature 80.5 %vth_ref 0c vtherm threshold with hysteresis (10c) 0c hyst increasing temperature 69.8 %vth_ref 10c vtherm threshold (10c) 10c decreasing temperature 69.8 %vth_ref 10c vtherm threshold with hysteresis (11c) 10c hyst increasing temperature 68.6 %vth_ref 45c vtherm threshold (45c) 45c increasing temperature 31.3 %vth_ref 45c vtherm threshold with hysteresis (44c) 45c hyst decreasing temperature 32.3 %vth_ref
zspm4551 datasheet ? 2016 integrated device technology, inc. 10 january 29, 2016 parameter symbol condition min typ max unit 50c vtherm threshold (50c) 50c increasing temperature 27.0 %vth_ref 50c vtherm threshold with hysteresis (49c) 50c hyst decreasing temperature 27.8 %vth_ref 60c vtherm threshold (60c) 60c increasing temperature 19.4 %vth_ref 60c vtherm threshold with hysteresis (50c) 60c hyst decreasing temperature 27.0 %vth_ref 1.5. i 2 c ? interface timing requirements electrical c haracteristics t j = - 40c to 125c, vin = 5.3v . see figure 2 . 5 for an illustration of the timing specifications given in table 1.5 . table 1 . 5 i 2 c ? interface timing characteristics parameter symbol standard mode fast mode 1) unit min max min max i 2 c ? c lock f requency f scl 0 100 0 400 khz i 2 c ? c lock h igh t ime t sch 4 0.6 s i 2 c ? c lock l ow t ime t scl 4.7 1.3 s i 2 c ? t olerable s pike t ime 2) t sp 0 50 0 50 ns i 2 c ? s erial d ata s etup t ime t sds 250 250 ns i 2 c ? s erial d ata h old t ime t sdh 0 0 s i 2 c ? i nput r ise t ime 2) t icr 1000 300 ns i 2 c ? i nput f all t ime 2) t icf 300 300 ns i 2 c ? o utput f all t ime; 10pf to 400 pf b us 2) t ocf 300 300 ns i 2 c ? b us f ree t ime b etween s top and start t buf 4.7 1.3 s i 2 c ? start or r epeated start c ondition s etup t ime t sts 4.7 0.6 s i 2 c ? start or r epeated start c ondition h old t ime t sth 4 0.6 s i 2 c ? stop c ondition s etup t ime 2) t sps 4 0.6 s 1) the i2c ? interface will operate in either standard or fast mode. 2) parameter not tested in production.
zspm4551 datasheet ? 2016 integrated device technology, inc. 11 january 29, 2016 2 functional description the zspm4551 is a fully - integrated li - ion battery charger ic based on a highly - efficient switching topology. it is configurable for termination voltage, charge current , and additional variables to allow optimum charging conditions for a wide range of li - ion batteries. a 1 mhz internal switching frequency facilitates lo w - cost lc filter combinations. figure 2 . 1 provides a block diagram for the zspm4551. figure 2 . 1 zspm4551 block diagram vin batt current control gate drive gate drive gate drive control vbat sw oscillator ramp generator comparator error amp gnd monitor & control batt thermal control over - voltage protection vbat vin vin s en pgnd nflt c out l out battery compensation network vth _ ref vtherm vref vbat r thm r ref r sense vsense current control scl sda vin vdd c vdd vdd regulator vin backgate blocking zspm 4551 i 2 c ? * interface i 2 c? * is a trademark of nxp . when the battery voltage is below 3.0 volts, the zspm4551 enters a pre - charge state and applies a small, programmable charge current to safely charge the battery to a level for which full - charge current can be applied. once the full - charge mode has been in itiated, the regulation will be for constant current (cc). when the battery voltage has increased enough to go into maintenance mode, the pwm control loop will force a constant voltage across the battery. once in constant voltage mode, current is monitored to determine when the battery is fully charged. see figure 2 . 2 for a diagram of the charging states.
zspm4551 datasheet ? 2016 integrated device technology, inc. 12 january 29, 2016 this regulation voltage as well as the 1c chargi ng current can be set to change based on the battery temperature. there are four temperature ranges for which the regulation voltage can be set independently: 0c to 10c, 10c to 45c, 45c to 50c, and 50c to 60c. the zspm4551 will stop charging if the temperature passes the descending temperature threshold at 0c or the ascending threshold at 60c. these thresholds have 10 degrees of hysteresis. the intermediate points have 1 degree of hysteresis. 2.1. internal protection 2.1.1. vin under - voltage lockout the devic e is held in the off state until the en pin voltage is high ( 2.2v) and vin rises to 3.15v (typical). there is a 200mv hysteresis on this input, which requires the input to fall below 2.95v (typical) before the device will disable. 2.1.2. internal current limit the current through the inductor l out is sensed on a cycle - by - cycle basis and if the current limit (i ocd ; see sec - tion 1.4 ) is reached, the zspm4551 will abbreviate the cycle. the c urrent limit is always active when the regulator is enabled. 2.1.3. thermal shutdown if the junction temperature of the zspm4551 exceeds 17 0c (typical), the sw output will tri - state to p rotect the device from damage. the n flt and all other protection circuitry will stay active to inform the system of the failure mode. once the device cools to 160c (typical), the device will attempt to start up again. if the device reaches 170c, the shutdown/restart sequence will repeat. 2.1.4. vbat over - voltage protection the zspm4551 has a battery protection circuit designed to shut down the charging profile if the battery voltage is greater than the termination voltage. the termination voltage can change based on user programming, so the protection threshold is set to 2% above the termination voltage. shutting down the charging profile puts the zspm4551 in a fault condition.
zspm4551 datasheet ? 2016 integrated device technology, inc. 13 january 29, 2016 2.2. fault handling 2.2.1. n flt pin functionality in the event of a battery over - voltage, the battery temperature being outside of the safe charging range , or the full charge timer expiring, charging stops , and the n flt pin is pulled low. when the fault condition is no longer present, the device will enter the initialize state (see figure 2 . 2 ) , but the n flt pin will remain low until the status register (0 0 hex ) is read (see table 2 . 2 ) . when the status register is read, the n flt pin will go high until a new fault is detect ed. 2.2.2. other faults when an open thermistor, thermal shut down, vin under - voltage, or top - off time - out are detected, charging immediately stop s and the corresponding bit in the status register (00 hex ) is set. the device enters the initialize state until the fault is no longer detected.
zspm4551 datasheet ? 2016 integrated device technology, inc. 14 january 29, 2016 figure 2 . 2 charging state diagram constant voltage mode full - charge constant current (cc) mode pre - charge state initialize state initialize waiting for valid charging conditions no pre - charge pre - charge current limit vbat > v prechg threshold yes no 1c charging 1c current limit and full - charge timer yes no faults & vbat < v restart vbat< v prechg threshold vbat = v termination & i charge < i eoc yes no yes no end of charge vbat regulated to v termination with eoc timer vbat = v termination no yes i charge < top off end current no en yes
zspm4551 datasheet ? 2016 integrated device technology, inc. 15 january 29, 2016 2.3. s erial i nterface the zspm4551 features an i 2 c ? slave interface that offers advanced c ontrol and diagnostic features. it supports standard and fast mode data rates and auto - sequencing, and it is compliant to i 2 c? standard version 3.0. i 2 c ? operation offers configuration control for termination voltages, charge currents, and charge timeouts. this configurability allows optimum charging conditions in a wide range of li - i on batteries. i 2 c ? operation also offers fault and warning indicators. wh enever a fault is detected, the associated status bit in the status register is set a nd the n flt pin is pulled low. whenever a warning is detected, the associated status bit in the status register is set, but t he n flt pin is not pulled low. reading the sta tus register resets the fault and warning status bits, and the n flt pin is released after all fault status bits have been reset. 2.3.1. i 2 c ? s ubaddress d efinition figure 2 . 3 subaddress in i 2 c ? transmission 2.3.2. i 2 c ? b us o peration the zspm4551 ?s i 2 c ? is a two - wire serial interfa ce; the two lines are serial cloc k (scl) and serial data (sda) (see figure 2 . 4 ) . sda must be connected to a positive supply (e.g., the vdd pin) through an external pull - up resistor. the devices communicating on this bus can drive the sda line low or release it to high impedance. to ensure proper operation, setup and hold times must be met (see table 1 . 5 ) . the device that initiates the i 2 c ? transaction becomes the master of the bus. communication is initiated by the master sending a sta rt condition, which is a high - to - low transition on sd a while the scl line is high. after the start condition, the device address byte is sent, most significant bit (msb) first, including the data direction bit ( read = 1; write = 0 ). after receiving the valid address byte, the device respo nds with an acknowledge (ack). an ack is a low on sda during the high of the ack - related clock pulse. on the i 2 c ? bus, during each clock pulse , onl y one data bit is transferred. the data on the sda line must remain stabl e during the high pulse of the clock period, as changes in the data line at this time are interpreted as start or stop control conditions . a low - to - high transition on sda while the scl input is high indicates a stop condition and is sent by the master .
zspm4551 datasheet ? 2016 integrated device technology, inc. 16 january 29, 2016 any number of data bytes can be transferred from the transmitter to receiver between the start and the stop conditions. each byte of eight bi ts is followed by one ack bit from the receiver . the sda line must be released by the transmitter before the receiv er can send an ack bit. the receiver that acknowledges must pull down the sda line during the ack clock pulse, so that the sda line is stable low during the high pulse of the ack - related clock period. when a slave receiver is addressed, it must generate an ack after each byte is received. similarly, the master must generate an ack after each byte that it receiv es from the slave transmitter. an end of data is signaled by the master receiver to the slave transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. this is done by the master receiver by holding the sda line high. the transmitter must then release the data line to enable the master to generate a stop condition. figure 2 . 4 i 2 c ? s tart / stop protocol see table 1 . 5 for the definitions and specifications for the timing parameters labeled in figure 2 . 5 . figure 2 . 5 i 2 c ? data transmission timing
zspm4551 datasheet ? 2016 integrated device technology, inc. 17 january 29, 2016 2.4. status and configuration registers table 2 . 1 register description s (device address = 48 hex ) register address name default description 0 00 hex status 00 hex status bit register 1 n/a n/a n/a register not implemented 2 02 hex config1 1) eeprom configuration register 3 03 hex config2 1) eeprom configuration register 4 04 hex config3 1) eeprom configuration register 5 05 hex config4 1) eeprom configuration register 6 06 hex config5 1) eeprom configuration register 7 -16 n/a n/a n/a registers not implemented 17 11 hex config_enable 00 hex enable configuration register access 18 12 hex eeprom_ctrl 1) 00 hex ee prom control register 1) config x and eeprom_ctrl registers are only accessible when the config_enable register is written with the en_cfg bit set to 1 (see table 2 . 8 ) . table 2 . 2 status register ? address 00 hex note: all of t he status register bits are read - only. data bit d7 d6 d5 d4 d3 d2 d1 d0 field name batt_ov 1c_to temp_0c temp_60c tsd top_to vin_uv th_open field name bit definition 1) batt_ov vbat over - voltage. 1c_to full charge timer has timed out . temp_0c thermistor indicates battery temperature < 0c . temp_60c thermistor indicates battery temperature > 60c . tsd thermal shutdown . top_to top -o ff timer has timed out . vin_uv vin under - voltage . th_open thermistor o pen (battery not present) . 1) faults are defined as batt_ov, 1c_to, temp_0c, and temp_60c. warnings are defined as tsd , top_to, vin_uv, and th_open. faults cause the n flt pin to be pulled low . warnings do not cause the n flt pin to be pulled low. all status bits are clear ed after status register read access. the n flt pin will go to high impedance (open - drain output) after the status register has been re ad and all status bits have been reset.
zspm4551 datasheet ? 2016 integrated device technology, inc. 18 january 29, 2016 table 2 . 3 configuration register config1 ? address 02 hex note: all of the config1 register bits are read/write . data bit d7 d6 d5 d4 d3 d2 d1 d0 field name pre_chrg[1:0] v_term_0_10[2:0] v_term_10_45[2:0] field name bit definition pre_chrg[1:0] 1) pre - charging configuration 00 bin ? 50 ma 01 bin ? 100 ma 10 bin ? 185 ma 11 bin ? 370 ma v_term_0_10[2:0] 2) voltage termination: 0 - 10c configuration 000 bin ? 3.94 v 001 bin ? 4.00 v 010 bin ? 4.05 v 011 bin ? 4.10 v 100 bin ? 4.12 v 101 bin ? 4.15 v 110 bin ? 4.18 v 111 bin ? invalid setting v_term_10_45[2:0] 2) voltage termination: 10- 45c configuration 1) pre_chrg note: maximum output current when v out < 3.0 v. 2) v_term note: there are separate settings for battery temperatures 0 - 10c, 10- 45c, 45 - 50c , and 50 - 60c (see table 2 . 4 for 45- 50c and 50- 60c) . for <0c and >60c, charging is disabled and a fault is set. table 2 . 4 configuration register config2 ? address 03 hex note: all of the config2 register bits are read/write. data bit d7 d6 d5 d4 d3 d2 d1 d0 field name eoc[1:0] v_term_45_50[2:0] v_term_50_60[2:0] field name bit definition eoc[1:0] 1) end of charge configuration 00 bin ? 50 ma 01 bin ? 100 ma 10 bin ? 185 ma 11 bin ? 370 ma v_term_45_50[2:0] 2) voltage termination: 45- 50c configuration 000 bin ? 3.94 v 001 bin ? 4.00 v 010 bin ? 4.05 v 011 bin ? 4.10 v 100 bin ? 4.12 v 101 bin ? 4.15 v 110 bin ? 4.18 v 111 bin ? invalid setting v_term_50_60[2:0] 2) voltage termination: 50- 60c configuration 1) eoc note: maximum output current when v out < 3.0 v. 2) v_term note: there are separate settings for battery temper atures 0 - 10c, 10 - 45c, 45 - 50c , and 50 - 60c (see table 2 . 3 for 0 - 10c and 10- 45c ). for <0c and >60c, charging is disa bled and a fault is set.
zspm4551 datasheet ? 2016 integrated device technology, inc. 19 january 29, 2016 table 2 . 5 co nfiguration register config3 ? address 04 hex note: all of the config3 register bits are read/write. data bit d7 d6 d5 d4 d3 d2 d1 d0 field name max_chrg_curr_0_10[3:0] max_chrg_curr_10_45[3:0] field name bit definition max_chrg_curr_0_10[3:0] 1) maximum charge current: 0 - 10c configuration 0000 bin ? 50 ma 0001 bin ? 100 ma 0010 bin ? 200 ma 0011 bin ? 300 ma 0100 bin ? 400 ma 0101 bin ? 500 ma 0110 bin ? 600 ma 0111 bin ? 700 ma 1000 bin ? 800 ma 1001 bin ? 900 ma 1010 bin ? 1000 ma 1011 bin ? 1100 ma 1100 bin ? 1200 ma 1101 bin ? 1300 ma 1110 bin ? 1400 ma 1111 bin ? 1500 ma max_chrg_curr_10_45[3:0] 1) maximum charge current; 10- 45c configuration 1) max_chrg_curr note: there are separate settings for battery temper atures 0 - 10c, 10 - 45c, 45 - 50c , and 50 - 60c (see table 2.6 for 45 - 50c and 50 - 60c). for <0c and >60c, charging is disabled and a fault is set. table 2 . 6 configuration register config4 ? address 05 hex note: all of the config4 register bits are read/write. data bit d7 d6 d5 d4 d3 d2 d1 d0 field name max_chrg_curr_45_50[3:0] max_chrg_curr_50_60[3:0] field name bit definition max_chrg_curr_45_50[3:0] 1) maximum charge current: 45- 50c configuration 0000 bin ? 50 ma 0001 bin ? 100 ma 0010 bin ? 200 ma 0011 bin ? 300 ma 0100 bin ? 400 ma 0101 bin ? 500 m a 0110 bin ? 600 ma 0111 bin ? 700 ma 1000 bin ? 800 ma 1001 bin ? 900 ma 1010 bin ? 1000 ma 1011 bin ? 1100 ma 1100 bin ? 1200 ma 1101 bin ? 1300 ma 1110 bin ? 1400 ma 1111 bin ? 1500 ma max_chrg_curr_50_60[3:0] 1) maximum charge current: 50- 60c configuration 1) max_chrg_curr note: there are separate settings for battery temperatures 0 - 10c, 10 - 45c, 45 - 50c , and 50 - 60c (see table 2.5 for 0 - 1 0c and 10- 45c). for <0c and >60c, charging is disabled and a fault is set.
zspm4551 datasheet ? 2016 integrated device technology, inc. 20 january 29, 2016 table 2 . 7 configuration register config5 ? address 06 hex note: all of the config5 register bits are read/write. data bit d7 d6 d5 d4 d3 d2 d1 d0 field name top_end th top_to[2:0] 1c_to[2:0] field name bit definition top_end 1) top -o ff end configuration 0 bin ? 25 ma 1 bin ? 92 ma th 2) thermistor configuratio n 0 bin ? 10k ? 1 bin ? 100k ? top_to[2:0] 3) top o ff timer time out configuration 000 bin ? 0 minutes 001 bin ? 20 minutes 010 bin ? 40 minutes 011 bin ? 60 minutes 100 bin ? 80 minutes 101 bin ? 100 minutes 110 bin ? 120 minutes 111 bin ? disable time out timer 1c_to[2:0] 4) full charge timer time out configuration 000 bin ? disable full charge timer 001 bin ? 200 minutes 010 bin ? 4 00 minutes 011 bin ? 600 minutes 100 bin ? 800 minutes 101 bin ? 1000 minutes 110 bin ? 1200 minutes 111 bin ? 1400 minutes 1) top_end note: charging stops when v v bat = v termination and i bat < top_end 2) th note: setting for nominal thermistor and reference resistor value. 3) top_to note: timer starts when vbat = v termination and i bat < eoc. 4) 1c_to note: timer starts when vbat > 3.0v.
zspm4551 datasheet ? 2016 integrated device technology, inc. 21 january 29, 2016 table 2 . 8 enable configuration register config_enable ? address 11 hex note: the reset value for all of the config_enable register bits is 0. not used not used not used not used not used not used not used en_cfg read/write r r r r r r r r/w field name bit definition en_cfg enable - access control bit for configuration registers config1 through config5 (addresses 02 hex to 06 hex ) 0 bin ? disable access 1 bin ? enable access table 2 . 9 eeprom control register eeprom_ctrl ? address 12 hex note: the reset value for all of the eeprom_ctrl register bits is 0. not used not used not used not used not used not used not used ee_prog read/write r r r r r r r r/w field name ee_prog 1) ee prom program control bit for configuration registers config1 through config5 (addresses 02 hex to 06 hex ) 0 bin ? disable ee prom programming 1 bin ? enable ee prom programming with da ta from configuration registers config1 through config5 (addresses 02 hex to 06 hex ) 1) ee_prog note: inputs vin and en must be present for 200 ms.
zspm4551 datasheet ? 2016 integrated device technology, inc. 22 january 29, 2016 c out l out r sense r ref battery r thm r pullup (optional) vdd r pullup (optional) vdd c vdd gnd en vtherm sw nflt vbat scl pgnd vin sda vth_ref vsense vdd zspm4551 c in 3 application circuits 3.1. typical application circuit figure 3 . 1 typical application circuit for charging a lithium -i on batter y 3.2. selection of external components note that the internal compensation is optimized for a 4.7 f output capacitor (c out ) and a 4.7 h output inductor (l out ). table 1 . 3 provides recommended ranges for most of the following components. 3.2.1. c out output capacitor to keep the output ripple low, a low esr (less than 35m ? ) ceramic capacitor is recommended for the 4.7 f output filter capacitor. the esr should not exceed 100m ?. 3.2.2. l out output inductor for best performance, an inductor with a saturation current rating higher than the maximum v out load requirement plus the inductor current ripple should be used for the 4.7 h output filter inductor. 3.2.3. c in bypass capacitor for best performance, a low esr ceramic capacitor should be used for the 10 f input supply bypass capacitor. if it is not a low esr ceramic capacitor, a 0.1 f ceramic capacitor should be added in parallel to c in . 3.2.4. c vdd bypass capacitor for vdd internal reference voltage output for best performance, a low esr ceramic capacitor should be used for the 100nf bypass capacitor from the vdd pin to ground.
zspm4551 datasheet ? 2016 integrated device technology, inc. 23 january 29, 2016 3.2.5. r sense output sensing resistor the typical value for the output sensing resistor is 50m ? . 3.2.6. pull - up resistors for proper function of the i 2 c ? interface, the sda pin must be connected to a positive supply (e.g., the vdd pin) through an external pull - up resistor. for proper function of the fault warning signal on the n flt pin, it must be connected to a positive supply (vdd) through an external pull - up resistor. 4 pin configuration and package 4.1. zspm4551 package dimensions figure 4 . 1 p qfn -16 p ackage d imensions
zspm4551 datasheet ? 2016 integrated device technology, inc. 24 january 29, 2016 4.2. pin - o ut assignments figure 4 . 2 zspm4551 pin assignments sw sda pgnd pgnd 13 14 15 16 vin sw vsense vbat 1 2 3 4 nflt vdd en gnd 8 7 6 5 vin scl vth_ref vtherm 12 11 10 9 zspm4551 pqfn16 4x4 top view 4.3. pin description for 16 - pin p qfn ( 4 x 4 mm ) table 4 . 1 pin d escription pin # name function description 1 sw switching voltage node connect to 4.7 h (typical) inductor l out . also connect to additional sw pin 14. 2 vin input voltage input voltage. also connect to c in . also connect to additional vin pin 11. 3 vsense current sense positive input positive input for the current loop. 4 vbat output voltage regulator f eedback i nput . 5 gnd gnd primary ground for the majority of the device except the low - side power fet. 6 en enable input when en is high ( 2.2v) , the device is en abled. ground the pin to disable the device. includes internal pull -up. 7 n flt inverted fault open - drain output. 8 vdd internal 3.3v supply output connect to a 100nf capacitor to gnd . 9 vtherm battery temperature sensor minus node negative node for the thermistor , which must be located in close proximity to the battery.
zspm4551 datasheet ? 2016 integrated device technology, inc. 25 january 29, 2016 pin # name function description 10 vth_ref battery temperature sensor positive node positive node for the thermistor , which must be located in close proximity to the battery . 11 vin input voltage additional vin pin for input voltage; connect to vin pin 2. 12 scl clock input i 2 c ? clock input. 13 sda data input/output i 2 c ? data ( open- drain output ) . 14 sw switching voltage node additional sw pin; connect to sw pin 1. 15 pgnd power gnd gnd supply for internal low - side fet/integrated diode. also connect to additional pgnd pin 16. 16 pgnd power gnd gnd supply for internal low - side fet/integrated diode. also connect to additional pgnd pin 15. 4.4. package markings figure 4 . 3 marking diagram 16 - pin p qfn (4 x 4 mm) xxxxx: lot number (last five digits) o: pin 1 mark yy: year ww: work week 45 51 a xxxxx oyyww
zspm4551 datasheet ? 2016 integrated device technology, inc. 26 january 29, 2016 5 layout recommendations to maximize the efficiency of this package for application on a single layer or multi - layer pcb, certain guidelines must be followed when laying out this part on the pcb. 5.1. multi - layer pcb layout the following are guidelines for mounting the exposed pad zspm4551 on a multi - layer pcb with ground a plane. in a multi - layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. the efficiency of this method depends on several factors, including die area, number of thermal vias, an d thickness of copper, etc. figure 5 . 1 package and pcb land configuration for multi - layer pcb package thermal pad solder pad ( land pattern ) thermal vias package outline figure 5 . 2 jedec standard fr4 multi - layer board ? cross - sectional view ( square ) package solder pad package solder pad ( bottom trace ) thermal via component traces thermal isolation power plane only 1 . 5748 mm 0 . 0 - 0 . 071 mm board base & bottom pad 0 . 5246 - 0 . 5606 mm power plane (1 oz cu ) 1 . 0142 - 1 . 0502 mm ground plane (1 oz cu ) 1 . 5038 - 1 . 5748 mm component trace (2 oz cu ) 2 plane 4 plane
zspm4551 datasheet ? 2016 integrated device technology, inc. 27 january 29, 2016 figure 5 . 3 is a representation of how the heat can be conducted away from the die using an exposed pad package. each application will have different requirements and limitations, and therefore the user should use sufficient copper to dissipate the power in the system. the output current rating for the linear regulators might need to be de - rated for ambient temperatures above 85 c. the de - rated value will depend on calculated worst case power dissipation and the thermal management implementation in the application. figure 5 . 3 conducting heat away from the die using an exposed pad package mold compound die epoxy die attach exposed pad solder thermal vias with cu plating single layer , 2 oz cu ground layer , 1 oz cu signal layer , 1 oz cu bottom layer , 2 oz cu 20 % cu coverage 90 % cu coverage 5 % - 10 % cu coverage note : not to scale . 5.2. single - layer pcb layout layout recommendations for a single - layer pcb: utilize as much copper area for power management as possible. in a single - layer board application, the thermal pad is attached to a heat spreader (copper areas) by using a low thermal impedance attachment method (sol der paste or thermal conductive epoxy). in both of the methods mentioned above, it is advisable to use as much copper trace as possible to dissipate the heat.
zspm4551 datasheet ? 2016 integrated device technology, inc. 28 january 29, 2016 figure 5 . 4 application using a single - layer pcb use as much copper area as possible for heat spread package thermal pad package outline important: if the attachment method is not implemented correctly, the functionality of the product is not guaranteed. power dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board. 6 ordering information ordering code description package zspm4551 aa1w zspm4551 high - efficiency charger for li - ion batter ies 16- pin pqfn / 7? reel (1000 parts) zspm4551 aa1r zspm4551 high - efficiency charger for li - ion batteries 16- pin pqfn / 13? reel (3300 parts) zspm4551 kit zspm4551 evaluation kit 7 related documents document zspm4551 feature sheet zspm4551 evaluation kit description zspm4551 application note ? li - ion battery charging applications visit idt ?s website www. idt .com or contact your nearest sales office for the latest version of these documents.
zspm4551 datasheet ? 2016 integrated device technology, inc. 29 january 29, 2016 8 document revision history revision date description 1.00 december 4, 2012 first r elease . 1.01 october 3, 2014 revision of specification for vth_ref output voltage in table 1 . 4 . updates for contact information and imagery on cover and headers. january 2 9 , 2016 changed to idt branding. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of user s. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united st ates and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossa ry . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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